// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_ap_sdi_axim_reg_c_union_define.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:02:59 Create file
// ******************************************************************************

#ifndef __HIPCIEC_AP_SDI_AXIM_REG_C_UNION_DEFINE_H__
#define __HIPCIEC_AP_SDI_AXIM_REG_C_UNION_DEFINE_H__

/* Define the union U_CTRL_SDI_SMMU_BYPASS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_0                     : 28  ; /* [31:4] */
        unsigned int    ctrl_iep_sdi1_smmu_bypass : 1  ; /* [3] */
        unsigned int    ctrl_iep_sdi0_smmu_bypass : 1  ; /* [2] */
        unsigned int    ctrl_iep_dma_smmu_bypass  : 1  ; /* [1] */
        unsigned int    ctrl_dma_smmu_bypass      : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_SDI_SMMU_BYPASS;

/* Define the union U_CTRL_SDI_ODR_MODE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_1               : 28  ; /* [31:4] */
        unsigned int    ctrl_pq_id_map_mode : 2  ; /* [3:2] */
        unsigned int    ctrl_pq_odr_mode    : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_SDI_ODR_MODE;

/* Define the union U_CTRL_SDI_ETH_CFG_ATTR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_2                : 27  ; /* [31:5] */
        unsigned int    ctrl_eth_cfg_snpattr : 1  ; /* [4] */
        unsigned int    ctrl_eth_cfg_cache   : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_SDI_ETH_CFG_ATTR;

/* Define the union U_CTRL_DMA_ATTR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_3              : 3  ; /* [31:29] */
        unsigned int    ctrl_dma_snpattr_3 : 1  ; /* [28] */
        unsigned int    ctrl_dma_cache_3   : 4  ; /* [27:24] */
        unsigned int    rsv_4              : 3  ; /* [23:21] */
        unsigned int    ctrl_dma_snpattr_2 : 1  ; /* [20] */
        unsigned int    ctrl_dma_cache_2   : 4  ; /* [19:16] */
        unsigned int    rsv_5              : 3  ; /* [15:13] */
        unsigned int    ctrl_dma_snpattr_1 : 1  ; /* [12] */
        unsigned int    ctrl_dma_cache_1   : 4  ; /* [11:8] */
        unsigned int    rsv_6              : 3  ; /* [7:5] */
        unsigned int    ctrl_dma_snpattr_0 : 1  ; /* [4] */
        unsigned int    ctrl_dma_cache_0   : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_DMA_ATTR;

/* Define the union U_CTRL_DMA_MEM_DAW_0_H */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_7                : 16  ; /* [31:16] */
        unsigned int    ctrl_dma_mem_daw_0_h : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_DMA_MEM_DAW_0_H;

/* Define the union U_CTRL_DMA_MEM_DAW_0_L */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    ctrl_dma_mem_dat_0_l : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_DMA_MEM_DAW_0_L;

/* Define the union U_CTRL_DMA_MEM_DAW_1_H */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_8                : 16  ; /* [31:16] */
        unsigned int    ctrl_dma_mem_daw_1_h : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_DMA_MEM_DAW_1_H;

/* Define the union U_CTRL_DMA_MEM_DAW_1_L */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    ctrl_dma_mem_dat_1_l : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_DMA_MEM_DAW_1_L;

/* Define the union U_CTRL_DMA_MEM_DAW_2_H */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_9                : 16  ; /* [31:16] */
        unsigned int    ctrl_dma_mem_daw_2_h : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_DMA_MEM_DAW_2_H;

/* Define the union U_CTRL_DMA_MEM_DAW_2_L */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    ctrl_dma_mem_dat_2_l : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_DMA_MEM_DAW_2_L;

/* Define the union U_CTRL_MCTP_ATTR_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_10              : 27  ; /* [31:5] */
        unsigned int    ctrl_mctp_snpattr_0 : 1  ; /* [4] */
        unsigned int    ctrl_mctp_cache_0   : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_MCTP_ATTR_0;

/* Define the union U_CTRL_MCTP_ATTR_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_11              : 27  ; /* [31:5] */
        unsigned int    ctrl_mctp_snpattr_1 : 1  ; /* [4] */
        unsigned int    ctrl_mctp_cache_1   : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_MCTP_ATTR_1;

/* Define the union U_CTRL_MCTP_ATTR_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_12              : 27  ; /* [31:5] */
        unsigned int    ctrl_mctp_snpattr_2 : 1  ; /* [4] */
        unsigned int    ctrl_mctp_cache_2   : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_MCTP_ATTR_2;

/* Define the union U_CTRL_MCTP_MEM_DAW_0_LL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    ctrl_mctp_mem_daw_0_ll : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_MCTP_MEM_DAW_0_LL;

/* Define the union U_CTRL_MCTP_MEM_DAW_0_LH */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_13                 : 16  ; /* [31:16] */
        unsigned int    ctrl_mctp_mem_daw_0_lh : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_MCTP_MEM_DAW_0_LH;

/* Define the union U_CTRL_MCTP_MEM_DAW_0_HL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    ctrl_mctp_mem_daw_0_hl : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_MCTP_MEM_DAW_0_HL;

/* Define the union U_CTRL_MCTP_MEM_DAW_0_HH */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_14                 : 16  ; /* [31:16] */
        unsigned int    ctrl_mctp_mem_daw_0_hh : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_MCTP_MEM_DAW_0_HH;

/* Define the union U_CTRL_MCTP_MEM_DAW_1_LL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    ctrl_mctp_mem_daw_1_ll : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_MCTP_MEM_DAW_1_LL;

/* Define the union U_CTRL_MCTP_MEM_DAW_1_LH */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_15                 : 16  ; /* [31:16] */
        unsigned int    ctrl_mctp_mem_daw_1_lh : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_MCTP_MEM_DAW_1_LH;

/* Define the union U_CTRL_MCTP_MEM_DAW_1_HL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    ctrl_mctp_mem_daw_1_hl : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_MCTP_MEM_DAW_1_HL;

/* Define the union U_CTRL_MCTP_MEM_DAW_1_HH */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_16                 : 16  ; /* [31:16] */
        unsigned int    ctrl_mctp_mem_daw_1_hh : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CTRL_MCTP_MEM_DAW_1_HH;

/* Define the union U_SDI_AXIM_INT_SRC */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_17                        : 25  ; /* [31:7] */
        unsigned int    int_src_axi_err_bresp_receive : 1  ; /* [6] */
        unsigned int    int_src_axi_err_rdata_receive : 1  ; /* [5] */
        unsigned int    int_src_axi_err_rresp_receive : 1  ; /* [4] */
        unsigned int    int_src_pq_sbm_ecc_mulbit     : 1  ; /* [3] */
        unsigned int    int_src_pq_sbm_ecc_onebit     : 1  ; /* [2] */
        unsigned int    int_src_npq_sbm_ecc_mulbit    : 1  ; /* [1] */
        unsigned int    int_src_npq_sbm_ecc_onebit    : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_INT_SRC;

/* Define the union U_SDI_AXIM_INT_MASK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    int_msk_sdi_axim              : 25  ; /* [31:7] */
        unsigned int    int_msk_axi_err_bresp_receive : 1  ; /* [6] */
        unsigned int    int_msk_axi_err_rdata_receive : 1  ; /* [5] */
        unsigned int    int_msk_axi_err_rresp_receive : 1  ; /* [4] */
        unsigned int    int_msk_pq_sbm_ecc_mulbit     : 1  ; /* [3] */
        unsigned int    int_msk_pq_sbm_ecc_onebit     : 1  ; /* [2] */
        unsigned int    int_msk_npq_sbm_ecc_mulbit    : 1  ; /* [1] */
        unsigned int    int_msk_npq_sbm_ecc_onebit    : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_INT_MASK;

/* Define the union U_SDI_AXIM_INT_STS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_18                        : 25  ; /* [31:7] */
        unsigned int    int_sts_axi_err_bresp_receive : 1  ; /* [6] */
        unsigned int    int_sts_axi_err_rdata_receive : 1  ; /* [5] */
        unsigned int    int_sts_axi_err_rresp_receive : 1  ; /* [4] */
        unsigned int    int_sts_pq_sbm_ecc_mulbit     : 1  ; /* [3] */
        unsigned int    int_sts_pq_sbm_ecc_onebit     : 1  ; /* [2] */
        unsigned int    int_sts_npq_sbm_ecc_mulbit    : 1  ; /* [1] */
        unsigned int    int_sts_npq_sbm_ecc_onebit    : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_INT_STS;

/* Define the union U_DFX_MEM_ECC_INJECT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_19                 : 28  ; /* [31:4] */
        unsigned int    dfx_pq_sbm_ecc_inject  : 2  ; /* [3:2] */
        unsigned int    dfx_npq_sbm_ecc_inject : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_MEM_ECC_INJECT;

/* Define the union U_DFX_NPQ_SBM_ECC_STATE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_20               : 16  ; /* [31:16] */
        unsigned int    dfx_npq_sbm_ecc_cnt  : 4  ; /* [15:12] */
        unsigned int    dfx_npq_sbm_ecc_addr : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_NPQ_SBM_ECC_STATE;

/* Define the union U_DFX_PQ_SBM_ECC_STATE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_21              : 16  ; /* [31:16] */
        unsigned int    dfx_pq_sbm_ecc_cnt  : 4  ; /* [15:12] */
        unsigned int    dfx_pq_sbm_ecc_addr : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_PQ_SBM_ECC_STATE;

/* Define the union U_DFX_NPQ_SBM_STATE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_22            : 15  ; /* [31:17] */
        unsigned int    dfx_npq_sbm_state : 17  ; /* [16:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_NPQ_SBM_STATE;

/* Define the union U_DFX_QUEUE_DISP_STATE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_23             : 4  ; /* [31:28] */
        unsigned int    dfx_pq_disp_state  : 12  ; /* [27:16] */
        unsigned int    rsv_24             : 4  ; /* [15:12] */
        unsigned int    dfx_npq_disp_state : 12  ; /* [11:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_QUEUE_DISP_STATE;

/* Define the union U_DFX_NPQ_PORT_STATE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_25             : 16  ; /* [31:16] */
        unsigned int    dfx_pq_port_state  : 8  ; /* [15:8] */
        unsigned int    dfx_npq_port_state : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_NPQ_PORT_STATE;

/* Define the union U_DFX_PQ_SEND_RO */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_pq_send_ro : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_PQ_SEND_RO;

/* Define the union U_DFX_PQ_SBM_RO_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_pq_sbm_ro_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_PQ_SBM_RO_0;

/* Define the union U_DFX_PQ_SBM_RO_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_pq_sbm_ro_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_PQ_SBM_RO_1;

/* Define the union U_DFX_NPQ_TBL_RO_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_npq_tbl_ro_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_NPQ_TBL_RO_0;

/* Define the union U_DFX_NPQ_TBL_RO_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_npq_tbl_ro_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_NPQ_TBL_RO_1;

/* Define the union U_DFX_NPQ_TBL_RO_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_npq_tbl_ro_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_NPQ_TBL_RO_2;

/* Define the union U_DFX_NPQ_TBL_RO_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_npq_tbl_ro_3 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_NPQ_TBL_RO_3;

/* Define the union U_DFX_PQ_TBL_RO_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_pq_tbl_ro_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_PQ_TBL_RO_0;

/* Define the union U_DFX_PQ_TBL_RO_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_pq_tbl_ro_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_PQ_TBL_RO_1;

/* Define the union U_DFX_PQ_TBL_RO_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_pq_tbl_ro_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_PQ_TBL_RO_2;

/* Define the union U_DFX_PQ_TBL_RO_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_pq_tbl_ro_3 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_PQ_TBL_RO_3;

/* Define the union U_DFX_NPQ_TBL_RD_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_26              : 23  ; /* [31:9] */
        unsigned int    dfx_npq_tbl_rd_en   : 1  ; /* [8] */
        unsigned int    dfx_npq_tbl_rd_qidx : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_NPQ_TBL_RD_REQ;

/* Define the union U_DFX_NPQ_TBL_RD_RO */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_npq_tbl_rd_ro : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_NPQ_TBL_RD_RO;

/* Define the union U_DFX_PQ_TBL_RD_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_27             : 23  ; /* [31:9] */
        unsigned int    dfx_pq_tbl_rd_en   : 1  ; /* [8] */
        unsigned int    dfx_pq_tbl_rd_qidx : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_PQ_TBL_RD_REQ;

/* Define the union U_DFX_PQ_TBL_RD_RO */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_pq_tbl_rd_ro : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_PQ_TBL_RD_RO;

/* Define the union U_DFX_HDR_BUF_RD_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_28               : 23  ; /* [31:9] */
        unsigned int    dfx_hdr_buf_rd_en    : 1  ; /* [8] */
        unsigned int    dfx_hdr_buf_rd_p_sel : 1  ; /* [7] */
        unsigned int    dfx_hdr_buf_rd_qidx  : 7  ; /* [6:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_HDR_BUF_RD_REQ;

/* Define the union U_DFX_HDR_BUF_RD_RO_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_hdr_buf_rd_ro_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_HDR_BUF_RD_RO_0;

/* Define the union U_DFX_HDR_BUF_RD_RO_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_hdr_buf_rd_ro_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_HDR_BUF_RD_RO_1;

/* Define the union U_DFX_HDR_BUF_RD_RO_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_hdr_buf_rd_ro_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_HDR_BUF_RD_RO_2;

/* Define the union U_DFX_TLB_ABORT_CNT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_29               : 16  ; /* [31:16] */
        unsigned int    dfx_tlb_abort_p_cnt  : 8  ; /* [15:8] */
        unsigned int    dfx_tlb_abort_np_cnt : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DFX_TLB_ABORT_CNT;

/* Define the union U_SDI_AXIM_GLOBAL_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_30                    : 23  ; /* [31:9] */
        unsigned int    ctrl_axuser_update_en     : 1  ; /* [8] */
        unsigned int    rsv_31                    : 2  ; /* [7:6] */
        unsigned int    ctrl_lat_stat_wr_en       : 1  ; /* [5] */
        unsigned int    ctrl_lat_stat_rd_en       : 1  ; /* [4] */
        unsigned int    ctrl_partial_write_64byte : 1  ; /* [3] */
        unsigned int    ctrl_en_wr_256byte        : 1  ; /* [2] */
        unsigned int    ctrl_en_rd_256byte        : 1  ; /* [1] */
        unsigned int    ctrl_shutdown_req         : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_GLOBAL_CTRL;

/* Define the union U_SDI_AXIM_MAX_TRANS_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_32            : 16  ; /* [31:16] */
        unsigned int    max_wr_trans_ctrl : 8  ; /* [15:8] */
        unsigned int    max_rd_trans_ctrl : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_MAX_TRANS_CTRL;

/* Define the union U_SDI_AXIM_QOS_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_33     : 24  ; /* [31:8] */
        unsigned int    awqos_ctrl : 4  ; /* [7:4] */
        unsigned int    arqos_ctrl : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_QOS_CTRL;

/* Define the union U_SDI_AXIM_ARUSER_MODE_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_34                   : 20  ; /* [31:12] */
        unsigned int    aruser_stash_mode        : 1  ; /* [11] */
        unsigned int    rsv_35                   : 1  ; /* [10] */
        unsigned int    aruser_type_mode         : 2  ; /* [9:8] */
        unsigned int    rsv_36                   : 1  ; /* [7] */
        unsigned int    rsv_37                   : 1  ; /* [6] */
        unsigned int    aruser_cleaninvalid_mode : 1  ; /* [5] */
        unsigned int    aruser_fna_mode          : 1  ; /* [4] */
        unsigned int    aruser_fa_mode           : 2  ; /* [3:2] */
        unsigned int    aruser_ssv_mode          : 1  ; /* [1] */
        unsigned int    aruser_strmid_mode       : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_ARUSER_MODE_CTRL;

/* Define the union U_SDI_AXIM_ARUSER_SET_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    aruser_strmid_set : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_ARUSER_SET_0;

/* Define the union U_SDI_AXIM_ARUSER_SET_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_38         : 15  ; /* [31:17] */
        unsigned int    aruser_ssv_set : 1  ; /* [16] */
        unsigned int    rsv_39         : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_ARUSER_SET_1;

/* Define the union U_SDI_AXIM_ARUSER_SET_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_40                  : 28  ; /* [31:4] */
        unsigned int    cfg_readclean_threshold : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_ARUSER_SET_2;

/* Define the union U_SDI_AXIM_AWUSER_MODE_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_41             : 20  ; /* [31:12] */
        unsigned int    awuser_stash_mode  : 1  ; /* [11] */
        unsigned int    awuser_so_mode     : 1  ; /* [10] */
        unsigned int    awuser_type_mode   : 2  ; /* [9:8] */
        unsigned int    rsv_42             : 1  ; /* [7] */
        unsigned int    awuser_fp_mode     : 1  ; /* [6] */
        unsigned int    rsv_43             : 1  ; /* [5] */
        unsigned int    awuser_fna_mode    : 1  ; /* [4] */
        unsigned int    awuser_fa_mode     : 2  ; /* [3:2] */
        unsigned int    awuser_ssv_mode    : 1  ; /* [1] */
        unsigned int    awuser_strmid_mode : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_AWUSER_MODE_CTRL;

/* Define the union U_SDI_AXIM_AWUSER_SET_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    awuser_strmid_set : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_AWUSER_SET_0;

/* Define the union U_SDI_AXIM_AWUSER_SET_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_44           : 15  ; /* [31:17] */
        unsigned int    awuser_ssv_set   : 1  ; /* [16] */
        unsigned int    awuser_so_set    : 4  ; /* [15:12] */
        unsigned int    rsv_45           : 1  ; /* [11] */
        unsigned int    awuser_stash_set : 11  ; /* [10:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_AWUSER_SET_1;

/* Define the union U_SDI_AXIM_AWUSER_SET_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_46                   : 24  ; /* [31:8] */
        unsigned int    cfg_so_violate_threshold : 4  ; /* [7:4] */
        unsigned int    rsv_47                   : 3  ; /* [3:1] */
        unsigned int    cfg_so_wr_optimize       : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_AWUSER_SET_2;

/* Define the union U_SDI_AXIM_DFX_MAX_TRANS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_48           : 16  ; /* [31:16] */
        unsigned int    dfx_max_wr_trans : 8  ; /* [15:8] */
        unsigned int    dfx_max_rd_trans : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_MAX_TRANS;

/* Define the union U_SDI_AXIM_DFX_WR_DAT_STS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_49                    : 27  ; /* [31:5] */
        unsigned int    dfx_wr_at_data_valid_sts  : 1  ; /* [4] */
        unsigned int    dfx_wr_odr_data_valid_sts : 1  ; /* [3] */
        unsigned int    dfx_wr_dat_wvalid_sts     : 1  ; /* [2] */
        unsigned int    dfx_odr_sbm_req_sts       : 1  ; /* [1] */
        unsigned int    dfx_wr_dat_req_sts        : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_WR_DAT_STS;

/* Define the union U_SDI_AXIM_DFX_AXI_RESP_ERR_STS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_50              : 28  ; /* [31:4] */
        unsigned int    dfx_wdata_error_sts : 1  ; /* [3] */
        unsigned int    dfx_bresp_error_sts : 1  ; /* [2] */
        unsigned int    dfx_rdata_error_sts : 1  ; /* [1] */
        unsigned int    dfx_rresp_error_sts : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_AXI_RESP_ERR_STS;

/* Define the union U_SDI_AXIM_DFX_AXI_GEN_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_wr_gen_req : 16  ; /* [31:16] */
        unsigned int    dfx_rd_gen_req : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_AXI_GEN_REQ;

/* Define the union U_SDI_AXIM_DFX_RD_TXID_STS_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    curr_rd_txid_sts_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_RD_TXID_STS_0;

/* Define the union U_SDI_AXIM_DFX_RD_TXID_STS_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    curr_rd_txid_sts_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_RD_TXID_STS_1;

/* Define the union U_SDI_AXIM_DFX_RD_TXID_STS_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    curr_rd_txid_sts_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_RD_TXID_STS_2;

/* Define the union U_SDI_AXIM_DFX_RD_TXID_STS_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    curr_rd_txid_sts_3 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_RD_TXID_STS_3;

/* Define the union U_SDI_AXIM_DFX_WR_TXID_STS_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    curr_wr_txid_sts_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_WR_TXID_STS_0;

/* Define the union U_SDI_AXIM_DFX_WR_TXID_STS_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    curr_wr_txid_sts_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_WR_TXID_STS_1;

/* Define the union U_SDI_AXIM_DFX_WR_TXID_STS_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    curr_wr_txid_sts_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_WR_TXID_STS_2;

/* Define the union U_SDI_AXIM_DFX_WR_TXID_STS_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    curr_wr_txid_sts_3 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_WR_TXID_STS_3;

/* Define the union U_SDI_AXIM_DFX_RRESP_CONFLICT_STS_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rresp_conflict_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_RRESP_CONFLICT_STS_0;

/* Define the union U_SDI_AXIM_DFX_RRESP_CONFLICT_STS_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rresp_conflict_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_RRESP_CONFLICT_STS_1;

/* Define the union U_SDI_AXIM_DFX_RRESP_CONFLICT_STS_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rresp_conflict_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_RRESP_CONFLICT_STS_2;

/* Define the union U_SDI_AXIM_DFX_RRESP_CONFLICT_STS_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rresp_conflict_3 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_RRESP_CONFLICT_STS_3;

/* Define the union U_SDI_AXIM_DFX_BRESP_CONFLICT_STS_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    bresp_conflict_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_BRESP_CONFLICT_STS_0;

/* Define the union U_SDI_AXIM_DFX_BRESP_CONFLICT_STS_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    bresp_conflict_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_BRESP_CONFLICT_STS_1;

/* Define the union U_SDI_AXIM_DFX_BRESP_CONFLICT_STS_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    bresp_conflict_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_BRESP_CONFLICT_STS_2;

/* Define the union U_SDI_AXIM_DFX_BRESP_CONFLICT_STS_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    bresp_conflict_3 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_BRESP_CONFLICT_STS_3;

/* Define the union U_SDI_AXIM_DFX_MEM_RD_LATENCY */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    max_mem_rd_latency : 16  ; /* [31:16] */
        unsigned int    ava_mem_rd_latency : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_MEM_RD_LATENCY;

/* Define the union U_SDI_AXIM_DFX_P2P_RD_LATENCY */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    max_p2p_rd_latency : 16  ; /* [31:16] */
        unsigned int    ava_p2p_rd_latency : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_P2P_RD_LATENCY;

/* Define the union U_SDI_AXIM_DFX_MEM_WR_LATENCY */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    max_mem_wr_latency : 16  ; /* [31:16] */
        unsigned int    ava_mem_wr_latency : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_MEM_WR_LATENCY;

/* Define the union U_SDI_AXIM_DFX_P2P_WR_LATENCY */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    max_p2p_wr_latency : 16  ; /* [31:16] */
        unsigned int    ava_p2p_wr_latency : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_P2P_WR_LATENCY;

/* Define the union U_SDI_AXIM_DFX_RD_TLP_PAYLOAD_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_rd_tlp_payload_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_RD_TLP_PAYLOAD_0;

/* Define the union U_SDI_AXIM_DFX_RD_TLP_PAYLOAD_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_rd_tlp_payload_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_RD_TLP_PAYLOAD_1;

/* Define the union U_SDI_AXIM_DFX_RD_TLP_PAYLOAD_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_rd_tlp_payload_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_RD_TLP_PAYLOAD_2;

/* Define the union U_SDI_AXIM_DFX_RD_TLP_PAYLOAD_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_rd_tlp_payload_3 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_RD_TLP_PAYLOAD_3;

/* Define the union U_SDI_AXIM_DFX_WR_TLP_PAYLOAD_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_wr_tlp_payload_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_WR_TLP_PAYLOAD_0;

/* Define the union U_SDI_AXIM_DFX_WR_TLP_PAYLOAD_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_wr_tlp_payload_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_WR_TLP_PAYLOAD_1;

/* Define the union U_SDI_AXIM_DFX_WR_TLP_PAYLOAD_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_wr_tlp_payload_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_WR_TLP_PAYLOAD_2;

/* Define the union U_SDI_AXIM_DFX_WR_TLP_PAYLOAD_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_wr_tlp_payload_3 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SDI_AXIM_DFX_WR_TLP_PAYLOAD_3;


//==============================================================================
/* Define the global struct */
typedef struct
{
    volatile U_CTRL_SDI_SMMU_BYPASS              CTRL_SDI_SMMU_BYPASS              ; /* 0 */
    volatile U_CTRL_SDI_ODR_MODE                 CTRL_SDI_ODR_MODE                 ; /* 4 */
    volatile U_CTRL_SDI_ETH_CFG_ATTR             CTRL_SDI_ETH_CFG_ATTR             ; /* 10 */
    volatile U_CTRL_DMA_ATTR                     CTRL_DMA_ATTR                     ; /* 20 */
    volatile U_CTRL_DMA_MEM_DAW_0_H              CTRL_DMA_MEM_DAW_0_H              ; /* 28 */
    volatile U_CTRL_DMA_MEM_DAW_0_L              CTRL_DMA_MEM_DAW_0_L              ; /* 2C */
    volatile U_CTRL_DMA_MEM_DAW_1_H              CTRL_DMA_MEM_DAW_1_H              ; /* 30 */
    volatile U_CTRL_DMA_MEM_DAW_1_L              CTRL_DMA_MEM_DAW_1_L              ; /* 34 */
    volatile U_CTRL_DMA_MEM_DAW_2_H              CTRL_DMA_MEM_DAW_2_H              ; /* 38 */
    volatile U_CTRL_DMA_MEM_DAW_2_L              CTRL_DMA_MEM_DAW_2_L              ; /* 3C */
    volatile U_CTRL_MCTP_ATTR_0                  CTRL_MCTP_ATTR_0                  ; /* 40 */
    volatile U_CTRL_MCTP_ATTR_1                  CTRL_MCTP_ATTR_1                  ; /* 44 */
    volatile U_CTRL_MCTP_ATTR_2                  CTRL_MCTP_ATTR_2                  ; /* 48 */
    volatile U_CTRL_MCTP_MEM_DAW_0_LL            CTRL_MCTP_MEM_DAW_0_LL            ; /* 50 */
    volatile U_CTRL_MCTP_MEM_DAW_0_LH            CTRL_MCTP_MEM_DAW_0_LH            ; /* 54 */
    volatile U_CTRL_MCTP_MEM_DAW_0_HL            CTRL_MCTP_MEM_DAW_0_HL            ; /* 58 */
    volatile U_CTRL_MCTP_MEM_DAW_0_HH            CTRL_MCTP_MEM_DAW_0_HH            ; /* 5C */
    volatile U_CTRL_MCTP_MEM_DAW_1_LL            CTRL_MCTP_MEM_DAW_1_LL            ; /* 60 */
    volatile U_CTRL_MCTP_MEM_DAW_1_LH            CTRL_MCTP_MEM_DAW_1_LH            ; /* 64 */
    volatile U_CTRL_MCTP_MEM_DAW_1_HL            CTRL_MCTP_MEM_DAW_1_HL            ; /* 68 */
    volatile U_CTRL_MCTP_MEM_DAW_1_HH            CTRL_MCTP_MEM_DAW_1_HH            ; /* 6C */
    volatile U_SDI_AXIM_INT_SRC                  SDI_AXIM_INT_SRC                  ; /* 80 */
    volatile U_SDI_AXIM_INT_MASK                 SDI_AXIM_INT_MASK                 ; /* 84 */
    volatile U_SDI_AXIM_INT_STS                  SDI_AXIM_INT_STS                  ; /* 8C */
    volatile U_DFX_MEM_ECC_INJECT                DFX_MEM_ECC_INJECT                ; /* 90 */
    volatile U_DFX_NPQ_SBM_ECC_STATE             DFX_NPQ_SBM_ECC_STATE             ; /* 100 */
    volatile U_DFX_PQ_SBM_ECC_STATE              DFX_PQ_SBM_ECC_STATE              ; /* 104 */
    volatile U_DFX_NPQ_SBM_STATE                 DFX_NPQ_SBM_STATE                 ; /* 108 */
    volatile U_DFX_QUEUE_DISP_STATE              DFX_QUEUE_DISP_STATE              ; /* 10C */
    volatile U_DFX_NPQ_PORT_STATE                DFX_NPQ_PORT_STATE                ; /* 110 */
    volatile U_DFX_PQ_SEND_RO                    DFX_PQ_SEND_RO                    ; /* 114 */
    volatile U_DFX_PQ_SBM_RO_0                   DFX_PQ_SBM_RO_0                   ; /* 118 */
    volatile U_DFX_PQ_SBM_RO_1                   DFX_PQ_SBM_RO_1                   ; /* 11C */
    volatile U_DFX_NPQ_TBL_RO_0                  DFX_NPQ_TBL_RO_0                  ; /* 120 */
    volatile U_DFX_NPQ_TBL_RO_1                  DFX_NPQ_TBL_RO_1                  ; /* 124 */
    volatile U_DFX_NPQ_TBL_RO_2                  DFX_NPQ_TBL_RO_2                  ; /* 128 */
    volatile U_DFX_NPQ_TBL_RO_3                  DFX_NPQ_TBL_RO_3                  ; /* 12C */
    volatile U_DFX_PQ_TBL_RO_0                   DFX_PQ_TBL_RO_0                   ; /* 130 */
    volatile U_DFX_PQ_TBL_RO_1                   DFX_PQ_TBL_RO_1                   ; /* 134 */
    volatile U_DFX_PQ_TBL_RO_2                   DFX_PQ_TBL_RO_2                   ; /* 138 */
    volatile U_DFX_PQ_TBL_RO_3                   DFX_PQ_TBL_RO_3                   ; /* 13C */
    volatile U_DFX_NPQ_TBL_RD_REQ                DFX_NPQ_TBL_RD_REQ                ; /* 140 */
    volatile U_DFX_NPQ_TBL_RD_RO                 DFX_NPQ_TBL_RD_RO                 ; /* 144 */
    volatile U_DFX_PQ_TBL_RD_REQ                 DFX_PQ_TBL_RD_REQ                 ; /* 148 */
    volatile U_DFX_PQ_TBL_RD_RO                  DFX_PQ_TBL_RD_RO                  ; /* 14C */
    volatile U_DFX_HDR_BUF_RD_REQ                DFX_HDR_BUF_RD_REQ                ; /* 150 */
    volatile U_DFX_HDR_BUF_RD_RO_0               DFX_HDR_BUF_RD_RO_0               ; /* 154 */
    volatile U_DFX_HDR_BUF_RD_RO_1               DFX_HDR_BUF_RD_RO_1               ; /* 158 */
    volatile U_DFX_HDR_BUF_RD_RO_2               DFX_HDR_BUF_RD_RO_2               ; /* 15C */
    volatile U_DFX_TLB_ABORT_CNT                 DFX_TLB_ABORT_CNT                 ; /* 160 */
    volatile U_SDI_AXIM_GLOBAL_CTRL              SDI_AXIM_GLOBAL_CTRL              ; /* 200 */
    volatile U_SDI_AXIM_MAX_TRANS_CTRL           SDI_AXIM_MAX_TRANS_CTRL           ; /* 204 */
    volatile U_SDI_AXIM_QOS_CTRL                 SDI_AXIM_QOS_CTRL                 ; /* 208 */
    volatile U_SDI_AXIM_ARUSER_MODE_CTRL         SDI_AXIM_ARUSER_MODE_CTRL         ; /* 220 */
    volatile U_SDI_AXIM_ARUSER_SET_0             SDI_AXIM_ARUSER_SET_0             ; /* 224 */
    volatile U_SDI_AXIM_ARUSER_SET_1             SDI_AXIM_ARUSER_SET_1             ; /* 228 */
    volatile U_SDI_AXIM_ARUSER_SET_2             SDI_AXIM_ARUSER_SET_2             ; /* 22C */
    volatile U_SDI_AXIM_AWUSER_MODE_CTRL         SDI_AXIM_AWUSER_MODE_CTRL         ; /* 230 */
    volatile U_SDI_AXIM_AWUSER_SET_0             SDI_AXIM_AWUSER_SET_0             ; /* 234 */
    volatile U_SDI_AXIM_AWUSER_SET_1             SDI_AXIM_AWUSER_SET_1             ; /* 238 */
    volatile U_SDI_AXIM_AWUSER_SET_2             SDI_AXIM_AWUSER_SET_2             ; /* 23C */
    volatile U_SDI_AXIM_DFX_MAX_TRANS            SDI_AXIM_DFX_MAX_TRANS            ; /* 280 */
    volatile U_SDI_AXIM_DFX_WR_DAT_STS           SDI_AXIM_DFX_WR_DAT_STS           ; /* 284 */
    volatile U_SDI_AXIM_DFX_AXI_RESP_ERR_STS     SDI_AXIM_DFX_AXI_RESP_ERR_STS     ; /* 288 */
    volatile U_SDI_AXIM_DFX_AXI_GEN_REQ          SDI_AXIM_DFX_AXI_GEN_REQ          ; /* 28C */
    volatile U_SDI_AXIM_DFX_RD_TXID_STS_0        SDI_AXIM_DFX_RD_TXID_STS_0        ; /* 290 */
    volatile U_SDI_AXIM_DFX_RD_TXID_STS_1        SDI_AXIM_DFX_RD_TXID_STS_1        ; /* 294 */
    volatile U_SDI_AXIM_DFX_RD_TXID_STS_2        SDI_AXIM_DFX_RD_TXID_STS_2        ; /* 298 */
    volatile U_SDI_AXIM_DFX_RD_TXID_STS_3        SDI_AXIM_DFX_RD_TXID_STS_3        ; /* 29C */
    volatile U_SDI_AXIM_DFX_WR_TXID_STS_0        SDI_AXIM_DFX_WR_TXID_STS_0        ; /* 2A0 */
    volatile U_SDI_AXIM_DFX_WR_TXID_STS_1        SDI_AXIM_DFX_WR_TXID_STS_1        ; /* 2A4 */
    volatile U_SDI_AXIM_DFX_WR_TXID_STS_2        SDI_AXIM_DFX_WR_TXID_STS_2        ; /* 2A8 */
    volatile U_SDI_AXIM_DFX_WR_TXID_STS_3        SDI_AXIM_DFX_WR_TXID_STS_3        ; /* 2AC */
    volatile U_SDI_AXIM_DFX_RRESP_CONFLICT_STS_0 SDI_AXIM_DFX_RRESP_CONFLICT_STS_0 ; /* 2B0 */
    volatile U_SDI_AXIM_DFX_RRESP_CONFLICT_STS_1 SDI_AXIM_DFX_RRESP_CONFLICT_STS_1 ; /* 2B4 */
    volatile U_SDI_AXIM_DFX_RRESP_CONFLICT_STS_2 SDI_AXIM_DFX_RRESP_CONFLICT_STS_2 ; /* 2B8 */
    volatile U_SDI_AXIM_DFX_RRESP_CONFLICT_STS_3 SDI_AXIM_DFX_RRESP_CONFLICT_STS_3 ; /* 2BC */
    volatile U_SDI_AXIM_DFX_BRESP_CONFLICT_STS_0 SDI_AXIM_DFX_BRESP_CONFLICT_STS_0 ; /* 2C0 */
    volatile U_SDI_AXIM_DFX_BRESP_CONFLICT_STS_1 SDI_AXIM_DFX_BRESP_CONFLICT_STS_1 ; /* 2C4 */
    volatile U_SDI_AXIM_DFX_BRESP_CONFLICT_STS_2 SDI_AXIM_DFX_BRESP_CONFLICT_STS_2 ; /* 2C8 */
    volatile U_SDI_AXIM_DFX_BRESP_CONFLICT_STS_3 SDI_AXIM_DFX_BRESP_CONFLICT_STS_3 ; /* 2CC */
    volatile U_SDI_AXIM_DFX_MEM_RD_LATENCY       SDI_AXIM_DFX_MEM_RD_LATENCY       ; /* 2D0 */
    volatile U_SDI_AXIM_DFX_P2P_RD_LATENCY       SDI_AXIM_DFX_P2P_RD_LATENCY       ; /* 2D4 */
    volatile U_SDI_AXIM_DFX_MEM_WR_LATENCY       SDI_AXIM_DFX_MEM_WR_LATENCY       ; /* 2D8 */
    volatile U_SDI_AXIM_DFX_P2P_WR_LATENCY       SDI_AXIM_DFX_P2P_WR_LATENCY       ; /* 2DC */
    volatile U_SDI_AXIM_DFX_RD_TLP_PAYLOAD_0     SDI_AXIM_DFX_RD_TLP_PAYLOAD_0     ; /* 2E0 */
    volatile U_SDI_AXIM_DFX_RD_TLP_PAYLOAD_1     SDI_AXIM_DFX_RD_TLP_PAYLOAD_1     ; /* 2E4 */
    volatile U_SDI_AXIM_DFX_RD_TLP_PAYLOAD_2     SDI_AXIM_DFX_RD_TLP_PAYLOAD_2     ; /* 2E8 */
    volatile U_SDI_AXIM_DFX_RD_TLP_PAYLOAD_3     SDI_AXIM_DFX_RD_TLP_PAYLOAD_3     ; /* 2EC */
    volatile U_SDI_AXIM_DFX_WR_TLP_PAYLOAD_0     SDI_AXIM_DFX_WR_TLP_PAYLOAD_0     ; /* 2F0 */
    volatile U_SDI_AXIM_DFX_WR_TLP_PAYLOAD_1     SDI_AXIM_DFX_WR_TLP_PAYLOAD_1     ; /* 2F4 */
    volatile U_SDI_AXIM_DFX_WR_TLP_PAYLOAD_2     SDI_AXIM_DFX_WR_TLP_PAYLOAD_2     ; /* 2F8 */
    volatile U_SDI_AXIM_DFX_WR_TLP_PAYLOAD_3     SDI_AXIM_DFX_WR_TLP_PAYLOAD_3     ; /* 2FC */

} S_hipciec_ap_sdi_axim_reg_REGS_TYPE;

/* Declare the struct pointor of the module hipciec_ap_sdi_axim_reg */
extern volatile S_hipciec_ap_sdi_axim_reg_REGS_TYPE *gophipciec_ap_sdi_axim_regAllReg;

/* Declare the functions that set the member value */
int iSetCTRL_SDI_SMMU_BYPASS_ctrl_iep_sdi1_smmu_bypass(unsigned int uctrl_iep_sdi1_smmu_bypass);
int iSetCTRL_SDI_SMMU_BYPASS_ctrl_iep_sdi0_smmu_bypass(unsigned int uctrl_iep_sdi0_smmu_bypass);
int iSetCTRL_SDI_SMMU_BYPASS_ctrl_iep_dma_smmu_bypass(unsigned int uctrl_iep_dma_smmu_bypass);
int iSetCTRL_SDI_SMMU_BYPASS_ctrl_dma_smmu_bypass(unsigned int uctrl_dma_smmu_bypass);
int iSetCTRL_SDI_ODR_MODE_ctrl_pq_id_map_mode(unsigned int uctrl_pq_id_map_mode);
int iSetCTRL_SDI_ODR_MODE_ctrl_pq_odr_mode(unsigned int uctrl_pq_odr_mode);
int iSetCTRL_SDI_ETH_CFG_ATTR_ctrl_eth_cfg_snpattr(unsigned int uctrl_eth_cfg_snpattr);
int iSetCTRL_SDI_ETH_CFG_ATTR_ctrl_eth_cfg_cache(unsigned int uctrl_eth_cfg_cache);
int iSetCTRL_DMA_ATTR_ctrl_dma_snpattr_3(unsigned int uctrl_dma_snpattr_3);
int iSetCTRL_DMA_ATTR_ctrl_dma_cache_3(unsigned int uctrl_dma_cache_3);
int iSetCTRL_DMA_ATTR_ctrl_dma_snpattr_2(unsigned int uctrl_dma_snpattr_2);
int iSetCTRL_DMA_ATTR_ctrl_dma_cache_2(unsigned int uctrl_dma_cache_2);
int iSetCTRL_DMA_ATTR_ctrl_dma_snpattr_1(unsigned int uctrl_dma_snpattr_1);
int iSetCTRL_DMA_ATTR_ctrl_dma_cache_1(unsigned int uctrl_dma_cache_1);
int iSetCTRL_DMA_ATTR_ctrl_dma_snpattr_0(unsigned int uctrl_dma_snpattr_0);
int iSetCTRL_DMA_ATTR_ctrl_dma_cache_0(unsigned int uctrl_dma_cache_0);
int iSetCTRL_DMA_MEM_DAW_0_H_ctrl_dma_mem_daw_0_h(unsigned int uctrl_dma_mem_daw_0_h);
int iSetCTRL_DMA_MEM_DAW_0_L_ctrl_dma_mem_dat_0_l(unsigned int uctrl_dma_mem_dat_0_l);
int iSetCTRL_DMA_MEM_DAW_1_H_ctrl_dma_mem_daw_1_h(unsigned int uctrl_dma_mem_daw_1_h);
int iSetCTRL_DMA_MEM_DAW_1_L_ctrl_dma_mem_dat_1_l(unsigned int uctrl_dma_mem_dat_1_l);
int iSetCTRL_DMA_MEM_DAW_2_H_ctrl_dma_mem_daw_2_h(unsigned int uctrl_dma_mem_daw_2_h);
int iSetCTRL_DMA_MEM_DAW_2_L_ctrl_dma_mem_dat_2_l(unsigned int uctrl_dma_mem_dat_2_l);
int iSetCTRL_MCTP_ATTR_0_ctrl_mctp_snpattr_0(unsigned int uctrl_mctp_snpattr_0);
int iSetCTRL_MCTP_ATTR_0_ctrl_mctp_cache_0(unsigned int uctrl_mctp_cache_0);
int iSetCTRL_MCTP_ATTR_1_ctrl_mctp_snpattr_1(unsigned int uctrl_mctp_snpattr_1);
int iSetCTRL_MCTP_ATTR_1_ctrl_mctp_cache_1(unsigned int uctrl_mctp_cache_1);
int iSetCTRL_MCTP_ATTR_2_ctrl_mctp_snpattr_2(unsigned int uctrl_mctp_snpattr_2);
int iSetCTRL_MCTP_ATTR_2_ctrl_mctp_cache_2(unsigned int uctrl_mctp_cache_2);
int iSetCTRL_MCTP_MEM_DAW_0_LL_ctrl_mctp_mem_daw_0_ll(unsigned int uctrl_mctp_mem_daw_0_ll);
int iSetCTRL_MCTP_MEM_DAW_0_LH_ctrl_mctp_mem_daw_0_lh(unsigned int uctrl_mctp_mem_daw_0_lh);
int iSetCTRL_MCTP_MEM_DAW_0_HL_ctrl_mctp_mem_daw_0_hl(unsigned int uctrl_mctp_mem_daw_0_hl);
int iSetCTRL_MCTP_MEM_DAW_0_HH_ctrl_mctp_mem_daw_0_hh(unsigned int uctrl_mctp_mem_daw_0_hh);
int iSetCTRL_MCTP_MEM_DAW_1_LL_ctrl_mctp_mem_daw_1_ll(unsigned int uctrl_mctp_mem_daw_1_ll);
int iSetCTRL_MCTP_MEM_DAW_1_LH_ctrl_mctp_mem_daw_1_lh(unsigned int uctrl_mctp_mem_daw_1_lh);
int iSetCTRL_MCTP_MEM_DAW_1_HL_ctrl_mctp_mem_daw_1_hl(unsigned int uctrl_mctp_mem_daw_1_hl);
int iSetCTRL_MCTP_MEM_DAW_1_HH_ctrl_mctp_mem_daw_1_hh(unsigned int uctrl_mctp_mem_daw_1_hh);
int iSetSDI_AXIM_INT_SRC_int_src_axi_err_bresp_receive(unsigned int uint_src_axi_err_bresp_receive);
int iSetSDI_AXIM_INT_SRC_int_src_axi_err_rdata_receive(unsigned int uint_src_axi_err_rdata_receive);
int iSetSDI_AXIM_INT_SRC_int_src_axi_err_rresp_receive(unsigned int uint_src_axi_err_rresp_receive);
int iSetSDI_AXIM_INT_SRC_int_src_pq_sbm_ecc_mulbit(unsigned int uint_src_pq_sbm_ecc_mulbit);
int iSetSDI_AXIM_INT_SRC_int_src_pq_sbm_ecc_onebit(unsigned int uint_src_pq_sbm_ecc_onebit);
int iSetSDI_AXIM_INT_SRC_int_src_npq_sbm_ecc_mulbit(unsigned int uint_src_npq_sbm_ecc_mulbit);
int iSetSDI_AXIM_INT_SRC_int_src_npq_sbm_ecc_onebit(unsigned int uint_src_npq_sbm_ecc_onebit);
int iSetSDI_AXIM_INT_MASK_int_msk_sdi_axim(unsigned int uint_msk_sdi_axim);
int iSetSDI_AXIM_INT_MASK_int_msk_axi_err_bresp_receive(unsigned int uint_msk_axi_err_bresp_receive);
int iSetSDI_AXIM_INT_MASK_int_msk_axi_err_rdata_receive(unsigned int uint_msk_axi_err_rdata_receive);
int iSetSDI_AXIM_INT_MASK_int_msk_axi_err_rresp_receive(unsigned int uint_msk_axi_err_rresp_receive);
int iSetSDI_AXIM_INT_MASK_int_msk_pq_sbm_ecc_mulbit(unsigned int uint_msk_pq_sbm_ecc_mulbit);
int iSetSDI_AXIM_INT_MASK_int_msk_pq_sbm_ecc_onebit(unsigned int uint_msk_pq_sbm_ecc_onebit);
int iSetSDI_AXIM_INT_MASK_int_msk_npq_sbm_ecc_mulbit(unsigned int uint_msk_npq_sbm_ecc_mulbit);
int iSetSDI_AXIM_INT_MASK_int_msk_npq_sbm_ecc_onebit(unsigned int uint_msk_npq_sbm_ecc_onebit);
int iSetSDI_AXIM_INT_STS_int_sts_axi_err_bresp_receive(unsigned int uint_sts_axi_err_bresp_receive);
int iSetSDI_AXIM_INT_STS_int_sts_axi_err_rdata_receive(unsigned int uint_sts_axi_err_rdata_receive);
int iSetSDI_AXIM_INT_STS_int_sts_axi_err_rresp_receive(unsigned int uint_sts_axi_err_rresp_receive);
int iSetSDI_AXIM_INT_STS_int_sts_pq_sbm_ecc_mulbit(unsigned int uint_sts_pq_sbm_ecc_mulbit);
int iSetSDI_AXIM_INT_STS_int_sts_pq_sbm_ecc_onebit(unsigned int uint_sts_pq_sbm_ecc_onebit);
int iSetSDI_AXIM_INT_STS_int_sts_npq_sbm_ecc_mulbit(unsigned int uint_sts_npq_sbm_ecc_mulbit);
int iSetSDI_AXIM_INT_STS_int_sts_npq_sbm_ecc_onebit(unsigned int uint_sts_npq_sbm_ecc_onebit);
int iSetDFX_MEM_ECC_INJECT_dfx_pq_sbm_ecc_inject(unsigned int udfx_pq_sbm_ecc_inject);
int iSetDFX_MEM_ECC_INJECT_dfx_npq_sbm_ecc_inject(unsigned int udfx_npq_sbm_ecc_inject);
int iSetDFX_NPQ_SBM_ECC_STATE_dfx_npq_sbm_ecc_cnt(unsigned int udfx_npq_sbm_ecc_cnt);
int iSetDFX_NPQ_SBM_ECC_STATE_dfx_npq_sbm_ecc_addr(unsigned int udfx_npq_sbm_ecc_addr);
int iSetDFX_PQ_SBM_ECC_STATE_dfx_pq_sbm_ecc_cnt(unsigned int udfx_pq_sbm_ecc_cnt);
int iSetDFX_PQ_SBM_ECC_STATE_dfx_pq_sbm_ecc_addr(unsigned int udfx_pq_sbm_ecc_addr);
int iSetDFX_NPQ_SBM_STATE_dfx_npq_sbm_state(unsigned int udfx_npq_sbm_state);
int iSetDFX_QUEUE_DISP_STATE_dfx_pq_disp_state(unsigned int udfx_pq_disp_state);
int iSetDFX_QUEUE_DISP_STATE_dfx_npq_disp_state(unsigned int udfx_npq_disp_state);
int iSetDFX_NPQ_PORT_STATE_dfx_pq_port_state(unsigned int udfx_pq_port_state);
int iSetDFX_NPQ_PORT_STATE_dfx_npq_port_state(unsigned int udfx_npq_port_state);
int iSetDFX_PQ_SEND_RO_dfx_pq_send_ro(unsigned int udfx_pq_send_ro);
int iSetDFX_PQ_SBM_RO_0_dfx_pq_sbm_ro_0(unsigned int udfx_pq_sbm_ro_0);
int iSetDFX_PQ_SBM_RO_1_dfx_pq_sbm_ro_1(unsigned int udfx_pq_sbm_ro_1);
int iSetDFX_NPQ_TBL_RO_0_dfx_npq_tbl_ro_0(unsigned int udfx_npq_tbl_ro_0);
int iSetDFX_NPQ_TBL_RO_1_dfx_npq_tbl_ro_1(unsigned int udfx_npq_tbl_ro_1);
int iSetDFX_NPQ_TBL_RO_2_dfx_npq_tbl_ro_2(unsigned int udfx_npq_tbl_ro_2);
int iSetDFX_NPQ_TBL_RO_3_dfx_npq_tbl_ro_3(unsigned int udfx_npq_tbl_ro_3);
int iSetDFX_PQ_TBL_RO_0_dfx_pq_tbl_ro_0(unsigned int udfx_pq_tbl_ro_0);
int iSetDFX_PQ_TBL_RO_1_dfx_pq_tbl_ro_1(unsigned int udfx_pq_tbl_ro_1);
int iSetDFX_PQ_TBL_RO_2_dfx_pq_tbl_ro_2(unsigned int udfx_pq_tbl_ro_2);
int iSetDFX_PQ_TBL_RO_3_dfx_pq_tbl_ro_3(unsigned int udfx_pq_tbl_ro_3);
int iSetDFX_NPQ_TBL_RD_REQ_dfx_npq_tbl_rd_en(unsigned int udfx_npq_tbl_rd_en);
int iSetDFX_NPQ_TBL_RD_REQ_dfx_npq_tbl_rd_qidx(unsigned int udfx_npq_tbl_rd_qidx);
int iSetDFX_NPQ_TBL_RD_RO_dfx_npq_tbl_rd_ro(unsigned int udfx_npq_tbl_rd_ro);
int iSetDFX_PQ_TBL_RD_REQ_dfx_pq_tbl_rd_en(unsigned int udfx_pq_tbl_rd_en);
int iSetDFX_PQ_TBL_RD_REQ_dfx_pq_tbl_rd_qidx(unsigned int udfx_pq_tbl_rd_qidx);
int iSetDFX_PQ_TBL_RD_RO_dfx_pq_tbl_rd_ro(unsigned int udfx_pq_tbl_rd_ro);
int iSetDFX_HDR_BUF_RD_REQ_dfx_hdr_buf_rd_en(unsigned int udfx_hdr_buf_rd_en);
int iSetDFX_HDR_BUF_RD_REQ_dfx_hdr_buf_rd_p_sel(unsigned int udfx_hdr_buf_rd_p_sel);
int iSetDFX_HDR_BUF_RD_REQ_dfx_hdr_buf_rd_qidx(unsigned int udfx_hdr_buf_rd_qidx);
int iSetDFX_HDR_BUF_RD_RO_0_dfx_hdr_buf_rd_ro_0(unsigned int udfx_hdr_buf_rd_ro_0);
int iSetDFX_HDR_BUF_RD_RO_1_dfx_hdr_buf_rd_ro_1(unsigned int udfx_hdr_buf_rd_ro_1);
int iSetDFX_HDR_BUF_RD_RO_2_dfx_hdr_buf_rd_ro_2(unsigned int udfx_hdr_buf_rd_ro_2);
int iSetDFX_TLB_ABORT_CNT_dfx_tlb_abort_p_cnt(unsigned int udfx_tlb_abort_p_cnt);
int iSetDFX_TLB_ABORT_CNT_dfx_tlb_abort_np_cnt(unsigned int udfx_tlb_abort_np_cnt);
int iSetSDI_AXIM_GLOBAL_CTRL_ctrl_axuser_update_en(unsigned int uctrl_axuser_update_en);
int iSetSDI_AXIM_GLOBAL_CTRL_ctrl_lat_stat_wr_en(unsigned int uctrl_lat_stat_wr_en);
int iSetSDI_AXIM_GLOBAL_CTRL_ctrl_lat_stat_rd_en(unsigned int uctrl_lat_stat_rd_en);
int iSetSDI_AXIM_GLOBAL_CTRL_ctrl_partial_write_64byte(unsigned int uctrl_partial_write_64byte);
int iSetSDI_AXIM_GLOBAL_CTRL_ctrl_en_wr_256byte(unsigned int uctrl_en_wr_256byte);
int iSetSDI_AXIM_GLOBAL_CTRL_ctrl_en_rd_256byte(unsigned int uctrl_en_rd_256byte);
int iSetSDI_AXIM_GLOBAL_CTRL_ctrl_shutdown_req(unsigned int uctrl_shutdown_req);
int iSetSDI_AXIM_MAX_TRANS_CTRL_max_wr_trans_ctrl(unsigned int umax_wr_trans_ctrl);
int iSetSDI_AXIM_MAX_TRANS_CTRL_max_rd_trans_ctrl(unsigned int umax_rd_trans_ctrl);
int iSetSDI_AXIM_QOS_CTRL_awqos_ctrl(unsigned int uawqos_ctrl);
int iSetSDI_AXIM_QOS_CTRL_arqos_ctrl(unsigned int uarqos_ctrl);
int iSetSDI_AXIM_ARUSER_MODE_CTRL_aruser_stash_mode(unsigned int uaruser_stash_mode);
int iSetSDI_AXIM_ARUSER_MODE_CTRL_aruser_type_mode(unsigned int uaruser_type_mode);
int iSetSDI_AXIM_ARUSER_MODE_CTRL_aruser_cleaninvalid_mode(unsigned int uaruser_cleaninvalid_mode);
int iSetSDI_AXIM_ARUSER_MODE_CTRL_aruser_fna_mode(unsigned int uaruser_fna_mode);
int iSetSDI_AXIM_ARUSER_MODE_CTRL_aruser_fa_mode(unsigned int uaruser_fa_mode);
int iSetSDI_AXIM_ARUSER_MODE_CTRL_aruser_ssv_mode(unsigned int uaruser_ssv_mode);
int iSetSDI_AXIM_ARUSER_MODE_CTRL_aruser_strmid_mode(unsigned int uaruser_strmid_mode);
int iSetSDI_AXIM_ARUSER_SET_0_aruser_strmid_set(unsigned int uaruser_strmid_set);
int iSetSDI_AXIM_ARUSER_SET_1_aruser_ssv_set(unsigned int uaruser_ssv_set);
int iSetSDI_AXIM_ARUSER_SET_2_cfg_readclean_threshold(unsigned int ucfg_readclean_threshold);
int iSetSDI_AXIM_AWUSER_MODE_CTRL_awuser_stash_mode(unsigned int uawuser_stash_mode);
int iSetSDI_AXIM_AWUSER_MODE_CTRL_awuser_so_mode(unsigned int uawuser_so_mode);
int iSetSDI_AXIM_AWUSER_MODE_CTRL_awuser_type_mode(unsigned int uawuser_type_mode);
int iSetSDI_AXIM_AWUSER_MODE_CTRL_awuser_fp_mode(unsigned int uawuser_fp_mode);
int iSetSDI_AXIM_AWUSER_MODE_CTRL_awuser_fna_mode(unsigned int uawuser_fna_mode);
int iSetSDI_AXIM_AWUSER_MODE_CTRL_awuser_fa_mode(unsigned int uawuser_fa_mode);
int iSetSDI_AXIM_AWUSER_MODE_CTRL_awuser_ssv_mode(unsigned int uawuser_ssv_mode);
int iSetSDI_AXIM_AWUSER_MODE_CTRL_awuser_strmid_mode(unsigned int uawuser_strmid_mode);
int iSetSDI_AXIM_AWUSER_SET_0_awuser_strmid_set(unsigned int uawuser_strmid_set);
int iSetSDI_AXIM_AWUSER_SET_1_awuser_ssv_set(unsigned int uawuser_ssv_set);
int iSetSDI_AXIM_AWUSER_SET_1_awuser_so_set(unsigned int uawuser_so_set);
int iSetSDI_AXIM_AWUSER_SET_1_awuser_stash_set(unsigned int uawuser_stash_set);
int iSetSDI_AXIM_AWUSER_SET_2_cfg_so_violate_threshold(unsigned int ucfg_so_violate_threshold);
int iSetSDI_AXIM_AWUSER_SET_2_cfg_so_wr_optimize(unsigned int ucfg_so_wr_optimize);
int iSetSDI_AXIM_DFX_MAX_TRANS_dfx_max_wr_trans(unsigned int udfx_max_wr_trans);
int iSetSDI_AXIM_DFX_MAX_TRANS_dfx_max_rd_trans(unsigned int udfx_max_rd_trans);
int iSetSDI_AXIM_DFX_WR_DAT_STS_dfx_wr_at_data_valid_sts(unsigned int udfx_wr_at_data_valid_sts);
int iSetSDI_AXIM_DFX_WR_DAT_STS_dfx_wr_odr_data_valid_sts(unsigned int udfx_wr_odr_data_valid_sts);
int iSetSDI_AXIM_DFX_WR_DAT_STS_dfx_wr_dat_wvalid_sts(unsigned int udfx_wr_dat_wvalid_sts);
int iSetSDI_AXIM_DFX_WR_DAT_STS_dfx_odr_sbm_req_sts(unsigned int udfx_odr_sbm_req_sts);
int iSetSDI_AXIM_DFX_WR_DAT_STS_dfx_wr_dat_req_sts(unsigned int udfx_wr_dat_req_sts);
int iSetSDI_AXIM_DFX_AXI_RESP_ERR_STS_dfx_wdata_error_sts(unsigned int udfx_wdata_error_sts);
int iSetSDI_AXIM_DFX_AXI_RESP_ERR_STS_dfx_bresp_error_sts(unsigned int udfx_bresp_error_sts);
int iSetSDI_AXIM_DFX_AXI_RESP_ERR_STS_dfx_rdata_error_sts(unsigned int udfx_rdata_error_sts);
int iSetSDI_AXIM_DFX_AXI_RESP_ERR_STS_dfx_rresp_error_sts(unsigned int udfx_rresp_error_sts);
int iSetSDI_AXIM_DFX_AXI_GEN_REQ_dfx_wr_gen_req(unsigned int udfx_wr_gen_req);
int iSetSDI_AXIM_DFX_AXI_GEN_REQ_dfx_rd_gen_req(unsigned int udfx_rd_gen_req);
int iSetSDI_AXIM_DFX_RD_TXID_STS_0_curr_rd_txid_sts_0(unsigned int ucurr_rd_txid_sts_0);
int iSetSDI_AXIM_DFX_RD_TXID_STS_1_curr_rd_txid_sts_1(unsigned int ucurr_rd_txid_sts_1);
int iSetSDI_AXIM_DFX_RD_TXID_STS_2_curr_rd_txid_sts_2(unsigned int ucurr_rd_txid_sts_2);
int iSetSDI_AXIM_DFX_RD_TXID_STS_3_curr_rd_txid_sts_3(unsigned int ucurr_rd_txid_sts_3);
int iSetSDI_AXIM_DFX_WR_TXID_STS_0_curr_wr_txid_sts_0(unsigned int ucurr_wr_txid_sts_0);
int iSetSDI_AXIM_DFX_WR_TXID_STS_1_curr_wr_txid_sts_1(unsigned int ucurr_wr_txid_sts_1);
int iSetSDI_AXIM_DFX_WR_TXID_STS_2_curr_wr_txid_sts_2(unsigned int ucurr_wr_txid_sts_2);
int iSetSDI_AXIM_DFX_WR_TXID_STS_3_curr_wr_txid_sts_3(unsigned int ucurr_wr_txid_sts_3);
int iSetSDI_AXIM_DFX_RRESP_CONFLICT_STS_0_rresp_conflict_0(unsigned int urresp_conflict_0);
int iSetSDI_AXIM_DFX_RRESP_CONFLICT_STS_1_rresp_conflict_1(unsigned int urresp_conflict_1);
int iSetSDI_AXIM_DFX_RRESP_CONFLICT_STS_2_rresp_conflict_2(unsigned int urresp_conflict_2);
int iSetSDI_AXIM_DFX_RRESP_CONFLICT_STS_3_rresp_conflict_3(unsigned int urresp_conflict_3);
int iSetSDI_AXIM_DFX_BRESP_CONFLICT_STS_0_bresp_conflict_0(unsigned int ubresp_conflict_0);
int iSetSDI_AXIM_DFX_BRESP_CONFLICT_STS_1_bresp_conflict_1(unsigned int ubresp_conflict_1);
int iSetSDI_AXIM_DFX_BRESP_CONFLICT_STS_2_bresp_conflict_2(unsigned int ubresp_conflict_2);
int iSetSDI_AXIM_DFX_BRESP_CONFLICT_STS_3_bresp_conflict_3(unsigned int ubresp_conflict_3);
int iSetSDI_AXIM_DFX_MEM_RD_LATENCY_max_mem_rd_latency(unsigned int umax_mem_rd_latency);
int iSetSDI_AXIM_DFX_MEM_RD_LATENCY_ava_mem_rd_latency(unsigned int uava_mem_rd_latency);
int iSetSDI_AXIM_DFX_P2P_RD_LATENCY_max_p2p_rd_latency(unsigned int umax_p2p_rd_latency);
int iSetSDI_AXIM_DFX_P2P_RD_LATENCY_ava_p2p_rd_latency(unsigned int uava_p2p_rd_latency);
int iSetSDI_AXIM_DFX_MEM_WR_LATENCY_max_mem_wr_latency(unsigned int umax_mem_wr_latency);
int iSetSDI_AXIM_DFX_MEM_WR_LATENCY_ava_mem_wr_latency(unsigned int uava_mem_wr_latency);
int iSetSDI_AXIM_DFX_P2P_WR_LATENCY_max_p2p_wr_latency(unsigned int umax_p2p_wr_latency);
int iSetSDI_AXIM_DFX_P2P_WR_LATENCY_ava_p2p_wr_latency(unsigned int uava_p2p_wr_latency);
int iSetSDI_AXIM_DFX_RD_TLP_PAYLOAD_0_dfx_rd_tlp_payload_0(unsigned int udfx_rd_tlp_payload_0);
int iSetSDI_AXIM_DFX_RD_TLP_PAYLOAD_1_dfx_rd_tlp_payload_1(unsigned int udfx_rd_tlp_payload_1);
int iSetSDI_AXIM_DFX_RD_TLP_PAYLOAD_2_dfx_rd_tlp_payload_2(unsigned int udfx_rd_tlp_payload_2);
int iSetSDI_AXIM_DFX_RD_TLP_PAYLOAD_3_dfx_rd_tlp_payload_3(unsigned int udfx_rd_tlp_payload_3);
int iSetSDI_AXIM_DFX_WR_TLP_PAYLOAD_0_dfx_wr_tlp_payload_0(unsigned int udfx_wr_tlp_payload_0);
int iSetSDI_AXIM_DFX_WR_TLP_PAYLOAD_1_dfx_wr_tlp_payload_1(unsigned int udfx_wr_tlp_payload_1);
int iSetSDI_AXIM_DFX_WR_TLP_PAYLOAD_2_dfx_wr_tlp_payload_2(unsigned int udfx_wr_tlp_payload_2);
int iSetSDI_AXIM_DFX_WR_TLP_PAYLOAD_3_dfx_wr_tlp_payload_3(unsigned int udfx_wr_tlp_payload_3);

#endif // __HIPCIEC_AP_SDI_AXIM_REG_C_UNION_DEFINE_H__
